1 ? icm7211am 4-digit, lcd display driver the icm7211am device is a non-multiplexed four-digit seven-segment cmos lcd display decoder-driver. this device is configured to drive conventional lcd displays by providing a complete rc oscillator, divider chain, backplane driver, and 28 segment outputs. it also has a microprocessor comp atible input configuration, which provides data input latches and digit address latches under control of high-speed chip select inputs. these devices simplify the task of implementing a cost-effective alphanumeric seven-segment display for microprocessor systems, without requiring extensive rom or cpu time for decoding and display updating. the icm7211am provides the ?code b? output code, i.e., 0-9, dash, e, h, l, p, blank, but will correctly decode true bcd to seven-segment decimal outputs. features ? four digit non-multiplexed 7 segment lcd display outputs with backplane driver ? complete onboard rc oscillator to generate backplane frequency ? backplane input/output allows simple synchronization of slave-devices to a master ? provides data and digit address latches controlled by chip select inputs to provide a direct high speed processor interface ? decodes binary to code b (0-9, dash, e, h, l, p, blank) ? pb-free plus anneal available (rohs compliant) ordering information part number part marking display type display decoding input interfacing display drive type temp. range (c) package pkg. dwg. # icm7211amlm44 icm7211amlm44 lcd code b microproces sor direct drive -40 to 85 44 ld mqfp q44.10x10 icm7211amlpl icm7211amlpl lcd code b microprocessor direct drive -40 to 85 40 ld pdip e40.6 ICM7211AMLPLZ (note) ICM7211AMLPLZ lcd code b microprocessor direct drive -40 to 85 40 ld pdip* (pb-free) e40.6 note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. *pb-free pdips can be used for through hole wa ve solder processing only. they are not intended for use in reflow solder process ing applications. caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2001, 2004-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. data sheet fn3158.7 april 17, 2006
2 fn3158.7 april 17, 2006 pinouts icm7211am (pdip) top view icm7211am (mqfp) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc v ss chip select 2 chip select 1 digit adress bit 2 digit adress bit 1 b3 b2 b1 b0 data inputs v dd e 1 g 1 f 1 bp a 2 b 2 c 2 d 2 e 2 g 2 f 2 a 3 b 3 c 3 d 3 e 3 g 3 f 3 a 4 d 1 c 1 b 1 a 1 f 4 g 4 e 4 d 4 c 4 b 4 nc e2 d2 c2 b2 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 g2 f2 a3 b3 c3 d3 e3 g3 f3 a4 nc 28 27 26 25 24 23 22 21 20 19 18 b4 c4 d4 e4 g4 f4 b0 b1 b2 b3 nc 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 nc d1 c1 b1 a1 osc v ss chip select 2 chip select 1 digital address bit 2 digital address bit 2 bp f1 g1 e1 v dd data inputs functional block diagram icm7211am 7 wide driver 7 wide latch en programmable 4 to 7 decoder 7 wide driver 7 wide latch en programmable 4 to 7 decoder 7 wide driver 7 wide latch en programmable 4 to 7 decoder 7 wide driver 7 wide latch en programmable 4 to 7 decoder d4 segment outputs d3 segment outputs d2 segment outputs d1 segment outputs 2-bit digit adress input chip chip data inputs oscillator input 2 to 4 decoder 2-bit latch enable 4-bit latch enable one shot select 1 select 2 blackplane driver enable oscillator 19khz free-running 128 enable director bp input/output icm7211am icm7211am
3 fn3158.7 april 17, 2006 absolute maximum ratings thermal information supply voltage (v dd - v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v input voltage (any terminal) (note 1) . . . v ss - 0.3v to v dd , + 0.3v operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to 85c thermal resistance (typical, note 2) ja (c/w) pdip package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . .-65c to 150c maximum lead temperature (soldering, 10s) . . . . . . . . . . . . 300c *pb-free pdips can be used for through hole wave solder process- ing only. they are not intended for use in reflow solder processing applications. caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. due to the scr structure inherent in the cmos proc ess, connecting any terminal to voltages greater than v dd or less than v ss may cause destructive device latchup. for th is reason, it is recommended that no inputs from external sources not operating on the same p ower supply be applied to the device before its s upply is established, and that in multiple supply systems, the supply to the icm7211am be tur ned on first. 2. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications parameter test conditions min typ max units characteristics v dd = 5v 10%, t a = 25c, v ss = 0v unless otherwise specified operating supply voltage range (v dd - v ss ), v supply 356 v operating current, i dd test circuit, display blank - 10 50 a oscillator input current, i osci pin 36 - 2 10 a segment rise/fall time, t r , t f c l = 200pf - 0.5 - s backplane rise/fall time, t r , t f c l = 5000pf - 1.5 - s oscillator frequency, f osc pin 36 floating - 19 - khz backplane frequency, f bp pin 36 floating - 150 - hz input characteristics logical ?1? input voltage, v ih 4- -v logical ?0? input voltage, v il --1v input leakage current, i ilk pins 27-34 - 0.01 1 a input capacitance, c ln pins 27-34 - 5 - pf bp/brightness input leakage, i bplk measured at pin 5 with pin 36 at v ss - 0.01 1 a bp/brightness input capacitance, c bpi all devices - 200 - pf ac characteristics chip select active pulse width, t wl other chip select either held active, or both driven together 200 - - ns data setup time, t ds 100 - - ns data hold time, t dh 10 0 - ns inter-chip select time, t ics 2- - s icm7211am icm7211am
4 fn3158.7 april 17, 2006 input definitions in this table, v dd and v ss are considered to be normal operating input logic levels. actual input low and high levels are specified under operating characteristics. for lowest power consumption, input signals should swing over the full supply. input dip terminal conditions function b0 27 v dd = logical one v ss = logical zero ones (least significant) data input bits b1 28 v dd = logical one v ss = logical zero twos b2 29 v dd = logical one v ss = logical zero fours b3 30 v dd = logical one v ss = logical zero eights (most significant) osc 36 floating or with external capacitor to v dd oscillator input v ss disables bp output devices, allowing segments to be synchronized to an external signal input at the bp terminal (pin 5). interface input configuration input description dip terminal conditions function da1 digit address bit 1 (lsb) 31 v dd = logical one v ss = logical zero da1 and da2 serve as a 2-bit digit address input da2, da1 = 00 selects d4 da2, da1 = 01 selects d3 da2, da1 = 10 selects d2 da2, da1 = 11 selects d1 da2 digit address bit 2 (msb) 32 v dd = logical one v ss = logical zero cs1 chip select 1 33 v dd = inactive v ss = active when both cs1 and cs2 are taken low, the data at the data and digit select code inputs are written into the input latches. on the rising edge of either chip select , the data is decoded and written into the output latches. cs2 chip select 2 34 v dd = inactive v ss = active timing diagram figure 1. microprocessor interface input cs1 (cs2) cs2 (cs1) data and digit address = don?t care t dh t ds t wi t ics icm7211am icm7211am
5 fn3158.7 april 17, 2006 typical performance curves figure 2. operating supply current as a function of supply voltage figure 3. backplane freq uency as a function of supply voltage v supp (v) 4 123 67 5 30 25 20 15 10 5 i op ( a) display blank, pin 36 open t a = -20c t a = 70c t a = 25c v supp (v) 4 123 6 5 180 150 120 90 60 30 ? bp (hz) t a = 25c 0 c osc = 220pf c osc = 22pf c osc = 0pf (pin 36 open) icm7211am icm7211am
6 fn3158.7 april 17, 2006 description of operation device the icm7211am provides outputs suitable for driving conventional four-digit, seven- segment lcd displays. these devices include 28 individual segment drivers, backplane driver, and a self-contained oscillator and divider chain to generate the backplane frequency. the segment and backplane dr ivers each consist of a cmos inverter, with the n-channel and p-channel devices ratioed to provide identical on resistances, and thus equal rise and fall times. this eliminates any dc component, which could arise from differing rise and fall times, and ensures maximum display life. the backplane output devices can be disabled by connecting the oscillator input (pin 36) to v ss . this allows the 28 segment outputs to be synchronized directly to a signal input at the bp terminal (pin 5). in this manner, several slave devices may be cascaded to the backplane output of one master device, or the backplane may be derived from an external source. this allows the use of displays with characters in multiples of four and a single backplane. a slave device represents a load of approximately 200pf (comparable to one additional segment). thus the limitation of the number of devices that can be slaved to one master device backplane driver is the additional load represented by the larger backplane of displays of more than four digits. a good rule of thumb to observe in order to minimize power consumption is to keep the backplane rise and fall times less than about 5 s. the backplane output driver should handle the backplane to a display of 16 one-half inch characters. it is recommended, if more than four devices are to be slaved together, the backplane signal be derived externally and all the icm7211am devices be slaved to it. this external signal should be capable of driving very large capacitive loads with short (1 - 2 s) rise and fall times. the maximum frequency for a backplane signal should be about 150hz although this may be too fast for optimum display response at lower display temperatures, depending on the display type. the onboard oscillator is designed to free run at approximately 19khz at microampere current levels. the oscillator frequency is divided by 128 to provide the backplane frequency, which will be approximately 150hz with the oscillator free-running; the oscillator frequency may be reduced by connecting an external capacitor between the oscillator terminal and v dd . the oscillator may also be overdriven if desired, although care must be taken to ensure that the backplane driver is not disabled during the negative port ion of the overdriving signal (which could cause a dc component to the display). this can be done by driving the oscillat or input between the positive supply and a level out of the range where the backplane disable is sensed (about one fifth of the supply voltage above v ss ). another technique for overdriving the oscillator (with a signal swinging the full supply) is to skew the duty cycle of the overdriving signal such that the negative portion has a duration shorter than about one microsec ond. the backplane disable sensing circuit will not respond to signals of this duration. input configurations and output codes the icm7211am accepts a four-bit true binary (i.e., positive level = logical one) input at pins 27 thru 30, least significant bit at pin 27 ascending to the most significant bit at pin 30. it decodes the binary input into seven-segment alphanumeric ?code b? output, i.e., 0-9, dash, e, h, l, p, blank. these codes are shown explicitly in ta ble 1. it will correctly decode true bcd to a seven-segment decimal output. table 1. output codes blnary code b icm7211am b3 b2 b1 bo 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 oscillator frequency backplane input/output off on 64 cycles 64 cycles 128 cycles segments segments figure 4. display waveforms icm7211am icm7211am
7 fn3158.7 april 17, 2006 the icm7211am is intended to accept data from a data bus under processor control. in these devices, the four data input bits and the two-bit digit address (da1 pin 31, da2 pin 32) are written into input buffer latches when both chip select inputs (cs1 pin 33, cs2 pin 34) are taken low. on the rising edge of either chip select input, the content of the data input latches is decoded and stored in the output latches of the digit selected by the contents of the digit address latches. an address of 00 writes into d4, da2 = 0, da1 = 1 writes into d3, da2 = 1, da1 = 0 writes into d2, and 11 writes into d1. the timing relationships for inputting data are shown in figure 1, and the chip select pulse widths and data setup and hold times are specified under operating characteristics. 1100 1101 1110 1111 blank table 1. output codes (continued) blnary code b icm7211am b3 b2 b1 bo a b c d f g e figure 5. segment assignment test circuit figure 6. 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 digit/chip icm7211am data inputs select inputs v ss osc v dd bp v dd v dd v ss microprocessor version multiplexed version each segment output to backplane with a 200pf capacitor + - v ss v dd icm7211am icm7211am
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn3158.7 april 17, 2006 typical application figure 7. 80c48 microprocessor interface 28 40 39 t1 p27 38 37 36 35 p17 34 33 32 31 30 29 p10 27 26 prog 22 24 23 p20 21 80c48 computer 2 xtal1 13 3 xtal2 4 reset 5 ss 6 int 7 ea rd db0 12 14 15 16 17 18 19 20 1 to psen ale v cc v dd v ss 11 9 25 db7 10 8 27 28 29 30 cs2 36 osc 35 v ss 1 v dd +5v 8 digit lcd display segments high order digits icm7211am input nc +5v i/o i/o ds1 ds2 cs1 31 32 33 34 data 2, 3, 4 bp 5 37-40 6-26 b0-b3 29 28 27 30 cs2 36 osc 35 v ss 1 v dd +5v segments low order digits icm7211am ds1 ds2 cs1 31 32 33 34 data 2, 3, 4 bp 5 37-40 6-26 b0-b3 wr icm7211am
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